FinFET EPI Channels Having Different Heights on a Stepped Substrate

ABSTRACT

A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.15/332,055, entitled “FinFET EPI Channels Having Different Heights on aStepped Substrate,” filed on Apr. 26, 2018, which application isincorporated herein by reference.

BACKGROUND

With the increasing down-scaling of integrated circuits and theincreasingly demanding requirements to the speed of integrated circuits,transistors need to have higher drive currents with increasingly smallerdimensions. Fin Field-Effect Transistors (FinFET) were thus developed.The FinFETs include vertical semiconductor fins above a substrate. Thesemiconductor fins are used to form source and drain regions, and toform channel regions between the source and drain regions. ShallowTrench Isolation (STI) regions are formed to define the semiconductorfins. The FinFETs also include gate stacks, which are formed on thesidewalls and the top surfaces of the semiconductor fins. Althoughexisting FinFET devices and methods of fabricating FinFET devices havebeen generally adequate for their intended purposes, they have not beenentirely satisfactory in all respects. For example, a more flexibleintegration for forming fin and isolation structures is desired.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1-8 illustrate cross-sectional views of intermediate stages in themanufacturing of fins of a FinFET, in accordance with some embodiments.

FIGS. 9-11 illustrate alternative arrangements of certain stages in themanufacturing of fins of a FinFET, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Fin Field-Effect Transistors (FinFETs) and methods of forming the sameare provided in accordance with various example embodiments. Theintermediate stages of forming the fins of a FinFET in accordance withsome embodiments are illustrated. Variations of the embodiments arediscussed. Throughout the various views and illustrative embodiments,like reference numbers are used to designate like elements.

FinFETs that have been epitaxially grown can be complex becausedifferent device types can require different fin materials. For example,a p-type fin can call for a growth of silicon germanium (SiGe), while ann-type fin can call for a growth of another semiconductor-based materialor less of silicon germanium than the p-type fin. The differences may bedue to the requirements of a punch through stop region at the base ofthe fin, where in a p-type fin subthreshold leakage current would tendto present a greater problem than in an n-type fin. Epitaxy of differentmaterials can result in different growth rates. Or even if the fins weremade of the same materials over a crystalline substrate, varying theheight of the epitaxy can be difficult for different fin types ordifferent fin applications.

Embodiments of the present disclosure allow for two or more fins of aFinFET device to be epitaxially grown on a substrate using the samematerials in each fin, but producing a different lattice constant in onefin verses the other and different strain profiles in each fin. Thisallows one fin to be used as an n-type fin in an n-type semiconductorarea of a semiconductor device and another fin to be used as a p-typefin in a p-type semiconductor area of a semiconductor device. A FinFETincluding n-type fins can be used to manufacture a p-channel metal oxidesemiconductor (PMOS) using a p-type doped substrate. A FinFET includingp-type fins can be used to manufacture an n-channel metal oxidesemiconductor (NMOS) using an n-type doped substrate. The two types offins (the NMOS and PMOS fins) can be used together to manufacture acomplimentary metal oxide semiconductor (CMOS) FinFET device. Further,although the two fins have different effective heights, their top mostsurfaces are aligned, thereby allowing for formation of other componentsof a FinFET as if the fins were the same height.

FIG. 1 illustrates a FinFET semiconductor structure at an early stage ofproduction. Semiconductor substrate 101 can be part of a semiconductorwafer or a semiconductor device. In accordance with some embodiments ofthe present disclosure, semiconductor substrate 101 includes crystallinesilicon. Other materials that can be used in the substrate 101 includecarbon, germanium, gallium, boron, arsenic, nitrogen, indium, and/orphosphorus, and the like. Semiconductor substrate 101 may also includeother semiconductor materials such as III-V compound semiconductormaterials. Semiconductor substrate 101 can be a bulk substrate or aSemiconductor-on-Insulator (SOI) substrate. Furthermore, the substrate101 may include other features. For example, the substrate may includevarious doped regions depending on design requirements (e.g., p-typesubstrate or n-type substrate). For example, the doped regions may bedoped with p-type dopants, such as boron or BF₂, n-type dopants, such asphosphorus or arsenic, and/or combinations thereof. The doped regionsmay be configured for an n-type FinFET, or alternatively configured fora p-type FinFET.

Element 105 of FIG. 1 illustrates the addition of a photoresist layer orsilicon oxide resist layer 105 that is deposited over substrate 101 andthen patterned, thereby forming openings in the resist layer 105.Generally, photolithography techniques utilize a photoresist material(such as photo resist 105) that is deposited, irradiated (exposed), anddeveloped to remove a portion of the photoresist material. The remainingphotoresist material protects the underlying material, such as thesubstrate 101 in this example, from subsequent processing steps, such asetching. In this example, the photoresist material is patterned todefine an area of the substrate 101 that will be etched and, conversely,an area of the substrate 101 that will be protected from etchant.

Referring to FIG. 2, the silicon substrate 101 is etched to form astepped substrate 103. Stepped substrate 103 can have a lower step 103 aand an upper step 103 b. The lower step 103 a has a height less than theheight of the upper step 103 b. The difference in the height of 103 aand 103 b is h1. The height h1 will vary by application. In someembodiments h1 is between about 15 nm and 100 nm, for example about 20nm. In other embodiments the step height difference h1 can be up to andincluding about 1 μm. The step height h1 can be optimized based ondifferent fin height requirements. The etchant used to etch opening 109in substrate 101 to form stepped substrate 103 can be a dry etch, a wetetch, a plasma etch and so forth. In some embodiments, the silicon etchcan be chlorine gas (Cl₂) or hydrogen bromide (HBr). Although ananisotropic etch is desirable, which can more closely result in thestepped substrate illustrated in FIG. 2, in some embodiments, the stepcan be angled toward or away from the upper step 103 b. In other wordsthe angle θ can be about 90 degrees for an anisotropic etch, asillustrated, or can be more or less than 90 degrees in some embodiments.For example, the angle θ can be in a range of about 75 degrees to about130 degrees, depending on the etchant used and step height h1.

Following the etching of the substrate 101 to form the stepped substrate103, photoresist mask layer 105 can be removed. Various techniques canbe used to remove photoresist mask layer 105, such as by a ChemicalMechanical Polish (CMP) process, photoresist solvent, or etch.

Turning to FIG. 3, a hard mask 113 can be disposed over the steppedsubstrate 103. The hard mask can be made of any suitable material thathas a high selectivity to etchants, such as silicon oxide (SiO), siliconnitride (SiN), or silicon oxycarbide (SiOC). Other suitable materialsfor hard mask 113 can include silicon carbide (SiC), Tantalum Nitride(TaN), Titanium Nitride (TiN), a low-k dielectric material (such asSiO2, SiOCH, borophosphosilicate glass (BPSG), TEOS, spin-on glass(SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG),high-density plasma (HDP) oxide, plasma-enhanced TEOS (PETEOS),fluorine-doped silicon oxide, carbon-doped silicon oxide, porous siliconoxide, porous carbon-doped silicon oxide, organic polymers, or siliconebased polymers), or spin-on carbon (SOC). In some embodiments, afterdeposition or formation of hard mask 113, a top surface of the hard mask113 can be planarized, for example, by a CMP process.

Hard mask 113 can be applied through a single step or multi-stepprocess. Such process(es) can include deposition, such as Sub AtomicChemical Vapor Deposition (SACVD), Flowable Chemical Vapor Deposition(FCVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD),and the like. In some embodiments, hard mask 115 can be applied as aliquid and then cured, heated, or annealed. For example, in embodimentswhere hard mask 113 is SOC, the SOC material may be dispensed as aliquid, and may be formed from raw materials that include elements suchas C, H, O, N, F, Br, and S. The SOC material may be between about 50%and about 95% carbon.

In some embodiments, hard mask 113 can be deposited in a first step tofill the opening 109 at a thickness of about h1 and in a second step toa thickness of about h2. The thickness h2 can be equal to or slightlymore than a desired minimum fin height, where the minimum fin height ismeasured from a top surface of the upper step 103 b of stepped substrate103 to a top surface of a completed fin.

A second resist layer 117 of FIG. 3 can be deposited over hard mask 113.Second resist layer 117 can be a photoresist layer that is depositedover hard mask 113 and then patterned, thereby forming openings 121 aand 121 b in the resist layer 117. The remaining photoresist materialprotects the underlying material, such as the hard mask 113, fromsubsequent processing steps, such as etching. The photoresist materialis patterned to define openings 121 a and 121 b, which correspond towhere fins will be formed over the stepped substrate 103.

Referring to FIG. 4a , using resist layer 117, recesses 125 a and 125 bcan be formed in hard mask 113. In some embodiments, such as illustratedin FIG. 4a , recess 125 a can be vertically aligned with the rise of thestep of stepped substrate 103, such that one side of recess 125 acomprises the rise of the step. In other embodiments, such asillustrated in FIG. 4b , recess 125 b can be vertically aligned with therise of the step of stepped substrate 103, such that one side of recess125 b coincides with the top edge of the upper step 103 b. In otherembodiments, such as illustrated in FIG. 4c , recesses 125 a and 125 bcan be situated on either side of a portion of hard mask 113 such thatneither is coincident with the step rise of stepped substrate 103. Insuch embodiments, the portion of hard mask 113 that lies between recess125 a and 125 b can overlap the step rise.

As illustrated in FIG. 5, a material 129 a and 129 b can be formedwithin the recess 125 a and 125 b. In some embodiments, the material canbe formed by epitaxial growth from the bottom of the recess, i.e., at anuppermost surface of the stepped substrate portion 113 a and anuppermost surface of the stepped substrate portion 113 b. The materialused in the formation of epitaxy 129 a and 129 b is the same in bothrecesses. Because the material formed in each recess is the same, thecost and complexity of growing the material 129 a and 129 b can bereduced. Also, because the material is the same, the growth rates of 129a and 129 b will be similar, subject to normal variations. This resultsin the height of material 129 a and 129 b being approximately the samewhen measured from the stepped substrate to an uppermost surface of eachof the respective materials 129 a and 129 b. As the material isepitaxially grown, the resulting material is crystalline. Because thestepped substrate 103 is comprised of crystalline silicon, it can helpseed the epitaxy materials 129 a and 129 b.

The height and width of the epitaxy materials 129 a and 129 b can dependon the application and fin technology. For example, the epitaxymaterials 129 a and 129 b can be grown to be about 25 nm to about 2 μmtall and about 5 nm to about 1 μm wide. A ratio of height to width canbe in a range of about 2:1 to about 10:1. For example, in someembodiments the height of the epitaxy materials 129 a and 129 b can beabout 30 nm and the width about 8 nm.

In some embodiments, the material in 129 a and 129 b is silicongermanium (SiGe). Other materials that can be used depending onapplication are pure germanium (Ge) or elements taken from groups III-Vor combinations and compositions thereof, and so forth.

In embodiments consistent with the structure illustrated in FIG. 4a ,the additional growth surface provided by the step rise of substrate 103can provide a larger lattice constant due to strain relaxation in thematerial 129 a grown in recess 125 a than the material 129 b grown inrecess 125 b.

Where the material 129 a has a larger lattice constant than the material129 b, the fins can be used differently. For example, in one embodiment,the fin comprising material 129 a can be used for an n-type transistorand the fin comprising material 129 b can be used for a p-typetransistor. The material 129 a can be considered a virtual substrate anda strain supplier for the material deposited thereon.

In other embodiments, the fins can be used in other configurationsaccording to a desired application.

Because the epitaxial growth of materials 129 a and 129 b is constrainedby hard mask 113 on either side of recess 125 a and 125 b, as materials129 a and 129 b epitaxially grow, outward lateral pressure (strain) canbe exhibited against hard mask 113. This outward pressure can cause orexacerbate an increased density of the hard mask 113 proximate to thegrowth area. In some embodiments, for example in FIG. 5, the left sideof hard mask portion 113 a will be affected to form higher densityportions of 113 a proximate to the material 129 a. Similarly, the rightside of hard mask portion 113 c will be affected to form higher densityportions of 113 c proximate to the material 129 b. Where the hard maskmaterial 113 b is between both material 129 a and 129 b, the density canbe even greater as pressure is exerted from both materials 129 a and 129b on hard mask 113 b.

Referring to FIG. 6, next semiconductor-based epitaxy 133 a and 133 bcan be epitaxially grown over materials 129 a and 129 b. Because therecess 125 a and 125 b of FIG. 5 have different depths, thesemiconductor-based epitaxy is overgrown in the recesses to form facetedportions 134 a and 134 b. The semiconductor-based epitaxy can bereferred to as a semiconductor epitaxy and can include materials such assilicon (Si), silicon geranium (SiGe), germanium (Ge), germanium alloyssuch as GeSn, and other group III-IV compounds. The epitaxy in 129 a and133 a are made of different materials. Using different materials withdifferent lattice constants will induce tensile/compressive stress inthe channel region. The width of the semiconductor-based epitaxy 133 aand 133 b will follow the profile of recess 125 a and 125 b and theheight of the semiconductor-based epitaxy 133 a and 133 b can be greaterthan the height of the depth of the recess 125 a and 125 b after theepitaxial growth of material 129 a and 129 b, such as illustrated inFIG. 5. In some embodiments, the semiconductor-based epitaxy 133 a maynot overgrow the recess 125 a.

As illustrated in FIG. 7, the top surface of the hard mask layer 113 canbe planarized to make a top surface of the semiconductor epitaxy 133 aand 133 b coplanar with each other and coplanar with hard mask layer113. Planarization can be accomplished, for example by a CMP process.Planarization can remove none or some of hard mask layer 113. In someembodiments, after planarization, the height h3 can be less than theheight h2 of FIG. 3. In other embodiments, after planarization, theheight h3 can be substantially equal to the height h2 of FIG. 3.

The epitaxy material 129 a and 129 b, such as SiGe, applies compressivestress to the adjacent area of the recess 125 a and 125 b with positivestrain values. The epitaxy material 129 a and 129 b also induces tensilestress to the upper area (the semiconductor-based epitaxy 133 a and 133b) with negative strain values. The induced tensile stress can result inmobility in the upper area of the channel 141 a. In the channel 141 bthe semiconductor-based epitaxy 133 b is much smaller in volume/heightthan the semiconductor-based epitaxy 133 a in the channel 141 a,resulting in a strain differential between the strainedsemiconductor-based epitaxy 133 a for an n-type fin (such as an NMOSfin) and the epitaxy material channel 129 b (e.g., SiGe) for a p-typefin (such as a PMOS fin). The semiconductor-based epitaxy cap 133 bremaining over the epitaxy material 129 b can provide a layer forincreased resiliency to high temperatures that can be subjected to theFinFET structure in subsequent steps, such as annealing.

Following planarization of the structure, as illustrated in FIG. 8, thehard mask material 113 can be removed to reveal fins 141 a and 141 b.The hard mask material 113 can be removed using an etchant. The etchantcan include a wet etchant or a dry etchant. In some embodiments, thesilicon etch can be an oxygen (O₂) plasma, N₂H₂ plasma, or othersuitable etchant. In some embodiments, the etchant can remove most ofthe hard mask material 113, however, some hard mask material 137 canremain behind. For example, in some embodiments, where the density ofthe hard mask material 113 was increased due to the epitaxy material 129a and 129 b of FIG. 5, some high density hard mask material 137 canremain behind. In some embodiments, all of the hard mask material 113can be removed.

In embodiments where high density hard mask 137 remains behind afteretching hard mask 113, the high density hard mask can act as anisolation region 137 with similar properties to a shallow trenchisolation (STI) region. In embodiments where all the hard mask materialis removed, an isolation material 137 can be deposited or formed betweenfins 141 a and 141 b.

In some embodiments, additional isolation material can be deposited (notshown), for example to the right side of fin 141 a and to the left sideof fin 141 b.

Although isolation region 137 is shown as having a flat top surfacewhich is coincidental to a transition between epitaxy material 129 a andsemiconductor epitaxy 133 a, in some embodiments the isolation region137 can have a curved top surface, for example a u-shaped top incross-section view. In some embodiments, the isolation region 137 canhave a height h5 with a top surface that is higher or lower than thetransition between epitaxy material 129 a and semiconductor epitaxy 133a. In some embodiments, where the top surface of the isolation region137 is lower than the transition between epitaxy material 129 a andsemiconductor epitaxy 133 a, additional isolation material can be addedover isolation region 137.

The resulting structure of FIG. 8 includes a first fin (channel) 141 aand a second fin (channel) 141 b. The fins have top surfaces that arealigned at a same height h4 from the lower step substrate 103 a topsurface. The overall height of the first fin 141 a is a height of h4.The overall height of the second fin 141 b is a height of h3. Each fincomprises a same material 129 a and 129 b, however 129 a and 129 b canhave different lattice constants. Each fin also comprises asemiconductor-based epitaxy 133 a and 133 b. An isolation region 137remains between the two fins. In some embodiments, the fin 141 a canform an NMOS strained silicon (Si) channel. The fin 141 b can form aPMOS silicon germanium (SiGe) channel (or other epitaxy materialchannel, depending on design and application).

By differentiating fin heights in different device regions, the junctionwindow is increased, which means that the fin heights of a FinFET indifferent device regions are no longer tied together. With the FinFEThaving different fin heights in different device regions, tuning theperformance of devices in different device regions can be more easilyaccomplished. For example, in one embodiment fin 141 a is an n-type finin a device region coincident with 103 a of the FinFET and fin 141 b isa p-type fin in a device region coincident with 103 b of the FinFET. Theeffective fin height h4 of n-type fin 141 a is greater than the finheight h3 of p-type fin 141 b. Accordingly, n-type fin 141 a and p-typefin 141 b may be used in a same logic area. For example, n-type fin 141a may be a pull-up transistor, and p-type fin 141 b may be a pull-downtransistor. The greater fin height of n-type fin 141 a may compensatefor the lower hole mobility compared to the higher electron mobility ofp-type fin 141 b. The performance of p-type fin 141 b and theperformance of n-type fin 141 a may thus be balanced.

In another example, in accordance with some embodiments, fin 141 a andfin 141 b can be used to manufacture a complementary metal oxidesemiconductor (CMOS) FinFET device. However, because each fin cancomprise the same materials, the complexity of manufacturing the CMOSdevice can be reduced. The CMOS device manufactured from the structurein FIG. 8 can have a semiconductor n-region defined by the lower step103 a of the stepped substrate 103 and a semiconductor p-region definedby the upper step 103 b of the stepped substrate 103. A boundary betweenthe n-region and p-region can be defined by the step rise.

In some embodiments, a CMOS device can be made from the structure inFIG. 8 by adding a gate insulator and gate over the fins andsource/drain regions. Because the tops of the fins 141 a and 141 b arealigned, the addition of other component parts of the FinFET can beaccomplished more easily than if the tops were not aligned.

It should be noted that while FIG. 8 shows the FinFET structure asincluding two fins (e.g., fins 141 a and 141 b), this is merely anexample. One skilled in the art will recognize there may be manymodifications, alternatives and variations. For example, thesemiconductor device of FIG. 8 may accommodate any number of finsdepending on different applications and design needs.

FIGS. 9-11 illustrate various other embodiments consistent with thedescription illustrating additional FinFET arrangements, in accordancewith some embodiments.

FIG. 9 illustrates a double CMOS structure according to someembodiments. The structure of FIG. 9 can be created in the same way aspreviously described. The structure of FIG. 9 includes a multi-steppedsubstrate 103. The substrate 103 can be made from a bulk crystallinesubstrate or other suitable substrate, as described above. A photoresistcan be disposed over the substrate above the 103 b portions and thesubstrate etched to produce a recess over the 103 a portion of thestepped substrate. The photoresist can be removed and a hard maskdisposed over the stepped substrate. The hard mask can be formed overthe substrate in a manner and of a material consist with that discussedabove with respect to FIG. 3. A resist layer can be disposed over thehard mask layer and patterned to form openings corresponding to the fins141 a and 141 b of FIG. 9.

The hard mask can be recessed down to the surfaces of the steppedsubstrate in a process consistent with that discussed above with respectto FIG. 4. A first epitaxy material 129 a and 129 b of FIG. 9 can begrown in each of the recesses in a process consistent with thatdiscussed above with respect to FIG. 5. The epitaxy material 129 a canhave a higher lattice constant than the epitaxy material 129 b. Asemiconductor-based epitaxy 133 a and 133 b can respectively be grownover 129 a and 129 b in a process consistent with that described abovewith respect to FIG. 6. The semiconductor-based epitaxy 133 a and 133 bcan overgrow the hard mask, forming a faceted structure above the hardmask. The structure can be planarized to remove the overgrowth and aligna top surface of 133 a and a top surface of 133 b.

The hard mask can then be removed. A high dense portion 147 can remainbehind between the fins 141 a and 141 b, such as described above withrespect to FIG. 8. The region defined by 103 a of FIG. 9 has a width w1.The width w1 can be wider or narrower than the perspective depicted. Forexample, FIG. 10 illustrates an alternative embodiment with a width w2which is much smaller than w1. Otherwise, the structure depicted in FIG.10 can be manufactured in a manner consistent with that of FIG. 9.

FIG. 11 illustrates a double CMOS structure according to someembodiments. The structure of FIG. 11 can be created in the same way aspreviously described above, for example, with respect to FIG. 9. Thestructure is similar to FIG. 9′s structure except the etched substrateportion 103 a appears on the outsides of the FinFET structure. Thestructure of FIG. 11 includes a multi-stepped substrate 103 and fourFinFET fins manufactured in a way similar to that described above withrespect to FIG. 9. The width in cross section of the substrate upperstep 103 b can be more or less than the perspective illustrated, similarto that described above with respect to the width of the lower step 103a in FIG. 10.

In some embodiments, embodiments consistent with the FIG. 9 and FIG. 11can be combined to form additional step substrate combinations.

Advantages of the present disclosure include providing a FinFETstructure capable of having different strain values in each fin, whilethe fins can be made from the same materials and in the same processsteps. Further, in some embodiments, the lattice constant in one fin canbe different than the lattice constant of the same material in anotherfin. The FinFET can be used to provide an n-type fin channel to providean NMOS and a p-type fin channel to provide a PMOS, which can be used toprovide a CMOS FinFET device. The resulting fin structure can havedifferent fin heights with different strain values and tensilestrengths. The fin structure can be used to create a semiconductordevice by adding a gate dielectric/insulator and gate materialperpendicular to and over the fins. Source/drain regions can be added.In some embodiments the source or drain regions of the fins can becoupled together depending on application.

In accordance with some embodiments, a structure can include a steppedcrystalline substrate that includes an upper step, a lower step, and astep rise. A first fin can include a crystalline structure having afirst lattice constant. The first fin can be formed over the lower step.A second fin can include a crystalline structure having a second latticeconstant, the second lattice constant being different than the firstlattice constant. The second fin can be formed over the upper step apartfrom the first fin.

In accordance with some embodiments, a semiconductor structure caninclude a first fin and a second fin. The first fin can have a firstheight as measured from a substrate. The second fin can have a secondheight as measured from the substrate. The first height can be greaterthan the second height. Or, in other words, the first fin can be tallerthan the second fin. The uppermost surface of the first fin can bealigned with the uppermost surface of the second fin.

In accordance with some embodiments, a method includes etching asubstrate to form a stepped substrate having an upper step and a lowerstep. A hard mask can be deposited over the stepped substrate. A firstand second recess can be formed in the hard mask, with the first recessbeing over the lower step and the second recess being over the upperstep. A first epitaxy material can be epitaxially grown in the first andsecond recess. The hard mask can be removed.

In accordance with some embodiments, a structure includes a first fin ofa crystalline structure having a first lattice constant, the first finformed over a lower step of a stepped substrate. The structure alsoincludes a second fin of a crystalline structure having a second latticeconstant, the second lattice constant being different than the firstlattice constant, the second fin formed over an upper step of thestepped substrate, apart from the first fin.

In accordance with some embodiments, a semiconductor structure includesa first fin having a first height as measured from a first upper surfaceof a stepped substrate. The semiconductor structure also includes asecond fin having a second height as measured from a second uppersurface of the stepped substrate, where the first height is greater thanthe second height, and an uppermost surface of the first fin is alignedwith an uppermost surface of the second fin.

In accordance with some embodiments, a device includes a first findisposed on a lower surface of a stepped substrate, the first finincluding a first epitaxial material and a second epitaxial materialover the first epitaxial material, the first epitaxial material having afirst thickness, the second epitaxial material having a secondthickness. The device also includes a second fin disposed on an uppersurface of a stepped substrate, the second fin adjacent the first fin,the second fin including a third epitaxial material, the third epitaxialmaterial having a third thickness, the first epitaxial material beingthe same as the third epitaxial material, the first thickness being thesame as the third thickness, where an upper surface of the firstepitaxial material is offset an upper surface of the third epitaxialmaterial.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A structure comprising: a first fin comprising acrystalline structure having a first lattice constant, the first finformed over a lower step of a stepped substrate; and a second fincomprising a crystalline structure having a second lattice constant, thesecond lattice constant being different than the first lattice constant,the second fin formed over an upper step of the stepped substrate, apartfrom the first fin.
 2. The structure of claim 1, wherein an uppermostsurface of the first fin is aligned with an uppermost surface of thesecond fin.
 3. The structure of claim 1, further comprising an isolationregion formed between the first fin and the second fin, the isolationregion comprising an insulating material.
 4. The structure of claim 1,wherein a side of the first fin is in contact with a step rise of thestepped substrate.
 5. The structure of claim 1, wherein the first fincomprises a first epitaxial material and wherein the second fincomprises the first epitaxial material.
 6. The structure of claim 5,wherein the first epitaxial material in the first fin has the firstlattice constant and the first epitaxial material in the second fin hasthe second lattice constant.
 7. The structure of claim 5, wherein thefirst fin comprises a second epitaxial material and wherein the secondfin comprises the second epitaxial material, wherein the secondepitaxial material is semiconductor-based.
 8. The structure of claim 7,wherein the first epitaxial material is silicon germanium (SiGe) and thesecond epitaxial material is silicon.
 9. The structure of claim 8,wherein the first fin comprises an n-type channel and the second fincomprises a p-type channel, wherein a height of the first fin is greaterthan a height of the second fin.
 10. A semiconductor structurecomprising: a first fin having a first height as measured from a firstupper surface of a stepped substrate; and a second fin having a secondheight as measured from a second upper surface of the stepped substrate,wherein the first height is greater than the second height, and anuppermost surface of the first fin is aligned with an uppermost surfaceof the second fin.
 11. The semiconductor structure of claim 10, whereinthe first fin and the second fin are comprised of the same materials.12. The semiconductor structure of claim 11, wherein the materials ofthe first fin and the materials of the second fin are epitaxialsemiconductor materials.
 13. The semiconductor structure of claim 10,wherein the first fin has a first lattice constant and the second finhas a second lattice constant, the first lattice constant beingdifferent from the second lattice constant.
 14. The semiconductorstructure of claim 10, wherein a first sidewall of the second fin isaligned with a step rise of the stepped substrate.
 15. The semiconductorstructure of claim 10, wherein the first fin comprises a first materialand a second material over the first material, wherein the second fincomprises the first material and the second material over the firstmaterial, wherein a first thickness of the first material in the firstfin is the same as a second thickness of the first material in thesecond fin, wherein a third thickness of the second material in thefirst fin is greater than a fourth thickness of the second material inthe second fin.
 16. A device comprising: a first fin disposed on a lowersurface of a stepped substrate, the first fin comprising a firstepitaxial material and a second epitaxial material over the firstepitaxial material, the first epitaxial material having a firstthickness, the second epitaxial material having a second thickness; anda second fin disposed on an upper surface of a stepped substrate, thesecond fin adjacent the first fin, the second fin comprising a thirdepitaxial material, the third epitaxial material having a thirdthickness, the first epitaxial material being the same as the thirdepitaxial material, the first thickness being the same as the thirdthickness, wherein an upper surface of the first epitaxial material isoffset an upper surface of the third epitaxial material.
 17. The deviceof claim 16, further comprising: an isolation region disposed betweenthe first fin and the second fin, the isolation region comprising alaterally compressed insulating material.
 18. The device of claim 16,wherein the second fin further comprises a fourth epitaxial materialover the third epitaxial material, the fourth epitaxial material havinga fourth thickness, the second epitaxial material being the same as thefourth epitaxial material, the second thickness being greater than thefourth thickness, wherein an upper surface of the second epitaxialmaterial is aligned to an upper surface of the fourth epitaxialmaterial.
 19. The device of claim 16, wherein a step rise of the steppedsubstrate is interposed between the first fin and the second fin, thestep rise is offset sidewalls of the first fin and offset sidewalls ofthe second fin.
 20. The device of claim 16, wherein the upper surface ofthe stepped substrate is a first upper surface, further comprising athird fin and a fourth fin, the third fin disposed on the lower surfaceof the stepped substrate, the fourth fin disposed on a second uppersurface of the stepped substrate, the third fin adjacent the fourth fin,wherein the first upper surface is aligned to the second upper surface.